Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other types of resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs.
PLDs typically have a limited supply of routing resources available to provide connections between components of the PLD. This differs from conventional application-specific integrated circuits (ASICs) in which almost any desired signal path may be custom-manufactured for a particular application. Existing approaches to PLD connection routing may fail to route all desired connections or may fail to meet the timing requirements of a particular design. In such cases, ripup and reroute operations are subsequently performed to remove routed connections and attempt to reroute them through alternative routing resources of the PLD. Such operations are inefficient, often result in degraded PLD performance, and significantly increase the time and processing resources needed to determine connection routings for the PLD.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.